i7SrSSKJr SSKJr SSKJrJrJrJ r J r SSK r SSK Jr \ (aSSKJrJr \"S 5r\"S 5R(R*rS rS r"S S5rg)ziUtilities for working with circuit schedule timing information returned from the Qiskit Runtime service.) annotations)cycle)TupleListSetDict TYPE_CHECKINGN) plotly_module)FigureScatterz.graph_objectsz.colorsAWGRbarrierc\rSrSrSrSSjr\SSj5rSSjrSSSjjr SSjr SS jr SS jr SS jr SS jrS rg)CircuitSchedule&zmThe class encapsulates the data of a Qiskit circuit schedule and contains the functionality to visualize it. cSUlSUlSUlURU5nUR U5 [ 5UlSUl0Ul/Ul [ 5Ul /Ul g)aInitialize a CircuitSchedule object with the schedule data generated by the compiler. The data is loaded as a single string of consecutive hardware instruction separated by new line arguments, parsed into a Numpy array to allow efficient filtration and preparation of the data for plotting. Args: circuit_schedule: A schedule data as a string of hardware instructions as returned by the compiler. Attributes: channels: A list of channels to be plotted (the rows in the plot). type_to_idx: A mapping from data type names to indices of the corresponding data in the circuit_scheduling Numpy array circuit_scheduling: A Numpy array container for holding and manipulating the data for plotting. instruction_set: A set of all the different instructions (gates + communication instructions) within the circuit scheduling. max_time: The duration of the scheduled circuit in cycles (a cycle is a global unit which may take a different amount of seconds on different backends). color_map: A color map for mapping instructions to colors. annotations: A list that contains annotations for traces. legend: A legend for the plot (a set of instructions). traces: A list of the plotly scatter traces to plot. N) channels type_to_idxcircuit_scheduling_load_parsesetinstruction_setmax_time color_maprlegendtraces)selfcircuit_scheduleraw_datas c/home/james-whalen/.local/lib/python3.13/site-packages/qiskit_ibm_runtime/utils/circuit_schedule.py__init__CircuitSchedule.__init__+sf8# +/"&::./ H),! )+') # %' ch[U[5(aURS5nU$[S5e)zLoad the data from a file or a data object. Args: circuit_schedule: A schedule data as a string of hardware instructions as returned by the compiler. Returns: Circuit schedule data.  zCircuitSchedule expects a str.) isinstancestrsplit TypeError)clsr datas r"rCircuitSchedule._loadUs7 & , ,#))$/D <= =r%c/nUHnUS:XaM URS5nSUS;aM'[U5S:wa [S5eURUSUSUSUS [ [ US 5[ US 5-5US USRS 5S/5 M /S Qn[ U5VVs0sHupgXv_M snnUl[R"U5Ul gs snnf)zParse the raw circuit schedule data into a numpy array. Args: raw_data: A list of instruction schedules as strings. Return: None. , shift_phaserzCannot interpret timeline data that doesn't have the format \ r _)Branch InstructionChannelStartFinishPulseGateNameN) r*len ValueErrorappendr)int enumeraternparrayr)rr!rlinewords data_namesidx data_names r"rCircuitSchedule._parsegs DrzJJsOEa(5zQ M  % %!H!H!H!HE!H E!H 56!H!HNN3'* ,b AJ:AVWAV~sINAVW"$((+=">Xs<C/NcUb^[U[5(aI[R"URSS2UR S4U5nURUUlU(aW[R RURSS2UR S4[5)nURUUlU(a;URSS2UR S4[:gnURUUlUR[R"URSS2UR S45Ul[R"URSS2UR S45Ul URR5 [UR5Ul [[URSS2UR S455Ul[R"URSS2UR S45Ul[%['UR"[)[*555Ulg)auPreprocess and filter the parsed circuit schedule data for visualization. Args: filter_awgr: If ``True``, remove all readout channels from scheduling data. filter_barriers: If ``True``, remove all barriers from scheduling data. included_channels: If not ``None``, remove all channels from scheduling data that are not in the ``included_channels`` list. Nr;r:r=r?)r(listrEisinrrchar startswithREADOUT_CHANNEL_PREFIXBARRIERargsortuniquersortrCmaxrrdictziprcolorsr)r filter_awgrfilter_barriersincluded_channelsmasks r" preprocessCircuitSchedule.preprocesss  (Z8I4-P-P77''4+;+;I+F(FGIZD'+&=&=d&CD # GG&&''4+;+;I+F(FGI_D'+&=&=d&CD # **1d.>.>}.M+MNRYYD&*&=&=d&CD #"&"9"9 JJt..q$2B2B92M/MN O#  $"9"9!T=M=Mi=X:X"YZ  T]]+ C 7 74;K;KH;U8U VWX !yy)@)@DDTDTU_D`A`)abc$"6"6f FGr%cHUS:XagUS:XagUS:Xag[SU35e)aoReturn y-axis trace shift for a finite duration instruction schedule and its annotation. The shifts are to distinguish static and dynamic (control-flow) parts of the circuit. Args: branch: The branch type to get the shift for, 'main' / 'then' / 'else'. Raises: ValueError for unsupported branch name. Returns: A y-axis shifts for trace and annotation. main)皙ٿ皙?rthen)rrdg?else)rcrgпUnexpected branch provided: rArbranchs r"!get_trace_finite_duration_y_shift1CircuitSchedule.get_trace_finite_duration_y_shifts8 V ! v ! v #;F8DE Er%cHUS:XagUS:XagUS:Xag[SU35e)aKReturn y-axis trace shift for a zero duration instruction schedule. The shifts are to distinguish static and dynamic (control-flow) parts of the circuit. Args: branch: The branch type to get the shift for, 'main' / 'then' / 'else'. Raises: ValueError for unsupported branch name. Returns: A y-axis shifts for trace. rbrre皙?rfgɿrgrhris r"get_trace_zero_duration_y_shift/CircuitSchedule.get_trace_zero_duration_y_shifts8 V  v  v ;F8DE Er%cUup#pEpgn[U5[U5peURU5upn URRU5n X-n X-nU[:Xa U S-n U S- n [ R UXV-S- UUXV-S- UUS/U U U UUUU S/SSUSRSU-SU-S [U5-S [U5-S [Xe- 5-/5US S 0SURUXR;S9 nURRU5 U[:XaSOUSU3nXV-S- X-SS SS.USS.nURRU5 g)zCreate a trace and annotation for a single finite duration instruction schedule. Args: instruction_schedule: A single instruction schedule as a numpy array. g?r Nmarkersx+text
Instruction: Pulse: Start: Finish: Duration: colorblacktoself xymode hoverinfonametext legendgrouprGfill fillcolor showlegendr0r8F rzsizerr~r showarrowfontr textangle)rCrkrindexrSgor joinr)rrrrBr)rinstruction_schedulerj instructionchannelt_it_fpulse gate_namey0y1 annotation_y channel_y_locy_lowy_hightracer annotations r"!trace_finite_duration_instruction1CircuitSchedule.trace_finite_duration_instructions FZBgC s8SXS $EEfM  ++G4 "#   $JB $JB  aa  #k1%C(S) 3sy>1 "7#nnY/ 3K& N 5!')r)AeW/E)q-%r2    +r%cUup#pEpgn[U5[U5peURU5n URRU5n X-n U S- n U S-n [R XUS-XUS- US/XXU S/SSUSR SU3SU3S U3S U3S Xe- 3/5US S 0SURUXR;S9 nURRU5 XV-S- U SS SS.USU3SS.nURRU5 g)zCreate a trace and annotation for a single zero duration instruction schedule. Args: instruction_schedule: A single instruction schedule as a numpy array. rnr4Nrrrsrtrurvrwrxryrzr{r|r}r Trrr8rr) rCrorrrr rrrrrBr)rrrjrrrrrry_shiftry_midrrrrs r"trace_zero_duration_instruction/CircuitSchedule.trace_zero_duration_instruction/sd FZBgC s8SXS66v> ++G4 '  !GS'35VE48#K=1eW%cUOse$  , "7#nnY/ 3' * 5!9/%r2 k5'*    +r%c~/nURHQnUu pEnSU;a.URU5 URRU5 M@UR U5 MS UH8nUu pFUR U5 URRU5 M: UR UR5 U$)zIterate through the processed circuit instruction schedules, generate their traces and annotations, and add those to the figure. Args: fig: A plotly figure to populate with traces. Return: The populated figure. r2)rrraddrBr add_tracesr)rfigshift_phase_instructionsrr8rrs r"populate_figureCircuitSchedule.populate_figurebs$& $($;$; 0D -Q1a9E)667KL  *)//0DE%<%= ,@ )Q1aA  0 01E F KKOOI &%= t{{# r%) rrrrrrrrr)r r))r r)return List[str])r!rrNone)FFN)r[boolr\rr]rNrr)rjr)rzTuple[float, float, float])rjr)rfloat)rznp.arrayrr)r PlotlyFigurerr)__name__ __module__ __qualname____firstlineno____doc__r# classmethodrrr_rkrorrr__static_attributes__r%r"rr&s((((T""?L" %"& )H)H)H )H  )HVF,F,K,Z1,fr%r)r __future__r itertoolsrtypingrrrrr numpyrEvisualization.utilsr plotly.graph_objectsr rr r qualitativePlotlyrZrRrSrrr%r"rsb$#88/D#$ y ! - - 4 4  ZZr%