z ikbSrSSKrSSKJr SSKJr SSKrSSKJ r J r J r J r J r JrJrJrJrJrJr SSKJrJrJr SSKJr SSKJrJrJr SS KJr SS K J!r! SS K"J#r$ S S K%J&r& Sr'S Sjr(S!Sjr)Sr*Sr+Sr,S"Sjr-Sr.Sr/\$R`RcS5S5r2Sr3S#Sjr4Sr5Sr6Sr7Sq8"SS\95r:g)$z'Common circuit visualization utilities.N) OrderedDict)warn) BoxOpClassicalRegisterClbit ControlFlowOpControlledGateDelayGate InstructionMeasureQuantumCircuitQubit)AnnotatedOperationInverseModifier PowerModifier)condition_resources)PauliEvolutionGatePhaseOracleGateBitFlipOracleGate)pi_check)circuit_to_dag) optionals)VisualizationErrorcX[U[[45=(a XR:H$N) isinstancerrlabel) gate_textops ]/home/james-whalen/.local/lib/python3.13/site-packages/qiskit/visualization/circuit/_utils.py_is_boolean_expressionr#,s# b?,=> ? YIQYQYDYYc US:Xa[U[5(agUS:Xa[U[5(ag/nSn[U[5(aUR(aURHvn[U[5(aUR S5 M+[U[ 5(dMBUR S[[URS55-S -5 Mx S RU5n[US S 5n[U5nS =n=p[US 5(aAURRnURR n [UR5n [US5(aUR"RnS n U (aU n Un OAU(a[U[$5(aUn Un O U(aUn OU(aUn O URn X:Xa UROU n US:wa>XS;a6USU SS:XaUSU SS:Xa USU n GO/SUSU S3n GO!US:Xa['X5(a)U R)SS5R)SS5n SU S3n OXR:XaU[*[,4;dX:Xa.U [*[,4;aU[.LaSU R15S3n O get_param_str..sD)z%,,)s')c3B# UHn[U[5v M g7fr)rrrWs r"rZr[sHiUz%00isr'r[]r2r&z...)outputndigitsz \,(\mathrm{,z})r,r8z$-$(r+) rAanyrSrr unit enumerater:r TypeErrorr;r>rC)r!rErb param_listcountrY param_strs r" get_param_strrlsr B ! ! D"))D D D HbiiH H H"e1ay23  %bii0LE'!eaiVu_QS!!%( .!!(5"QR1I W (*)=(>cBI  u_99Z01::3FI CHHZ013I  .!!#e*- .sE$E?>E?cSnSn0nUHXn[X5nUb[U[5(aU(d XEU'US- nM8UcM=U(dMFXs:wdMMUnXEU'US- nMZ U$)aMap the bits and registers to the index from the top of the drawing. The key to the dict is either the (Qubit, Clbit) or if cregbundle True, the register that is being bundled. Args: circuit (QuantumCircuit): the circuit being drawn bits (list(Qubit, Clbit)): the Qubit's and Clbit's in the circuit cregbundle (bool): if True bundle classical registers. Default: ``True``. Returns: dict((Qubit, Clbit, ClassicalRegister): index): map of bits/registers to index Nrr*)get_bit_registerrr)circuitbits cregbundleprev_reg wire_indexwire_mapbitregisters r" get_wire_maprwswHJH#G1  :c5#9#9&SM !OJ  !jjX5IH!+X  !OJ Or$cnURU5nUR(aURSS$S$)zGet the register for a bit if there is one Args: circuit (QuantumCircuit): the circuit being drawn bit (Qubit, Clbit): the bit to use to find the register and indexes Returns: ClassicalRegister: register associated with the bit rN)find_bit registers)rorubit_locs r"rnrns7s#G&-&7&77  Q  "ATAr$cURU5nURnUR(aURSOSupEXCU4$)aGet the register for a bit if there is one, and the index of the bit from the top of the circuit, or the index of the bit within a register. Args: circuit (QuantumCircuit): the circuit being drawn bit (Qubit, Clbit): the bit to use to find the register and indexes Returns: (ClassicalRegister, None): register associated with the bit int: index of the bit from the top of the circuit int: index of the bit within the register, if there is a register r)NN)ryindexrz)rorur{ bit_indexrv reg_indexs r"get_bit_reg_indexrsEs#G I292C2C'++A.H  ))r$c ^ US:XaUOSUS3nUcUnU$US:XaURnURSU3nO!S[UR5S3nUSUS3n[U[5(a;U(aUS:waURnU$URS:XdU(aUnU$UnU$URS:XaUnU$UcUnU$X2(aX2m [ U 4S jUR 555n US:Xa'U RSU SSRT 5S U3nO)SU RS U SSRT 5S US3nUS:waURSS5nU$UnU$![a T RbdT Rn US:Xa(U RSU SSRT 5S U3nNoSU RS U SSRT 5S US3nNUS:Xa US U3nNUS US3nNf=f)aGet the bit labels to display to the left of the wires. Args: drawer (str): which drawer is calling ("text", "mpl", or "latex") register (QuantumRegister or ClassicalRegister): get wire_label for this register index (int): index of bit in register layout (Layout): Optional. mapping of virtual to physical bits cregbundle (bool): Optional. if set True bundle classical registers. Default: ``True``. Returns: str: label to display for the register/index r({}Nr5z_{r2r*c38># UHnTU;dM Uv M g7fr)rXregvirt_bits r"rZ!get_wire_label..sU+ACXQT_CC+A  z -> z}_{z } \mapsto {z \mapsto { \;) rBfix_special_charactersrrsizenext get_registersr} StopIteration _registerrC) rErvr}layoutrq index_str wire_labelreg_namereg_name_indexvirt_regrs @r"get_wire_labelrs%.5'brNI  mm_$MM?!E73.x}}=>bA$:Sr2(-.. &G+$MM?J  ==A !J(J}} D C # @ ? = EU6+?+?+AUUH ( a 0A0A(0K/LDQVPWX uXa[->->x-H,IX]W^^`a& V #++C7J  + E!!-#--V#$,MM?!HQK4E4Eh4O3PPTUZT[!\JX]]O,%a[..x89:&&+WB0 V#$-;d5'!:J$-;l5'!DJ Es,AE.'(E..AH?(H) H8HHc[[US[55n[US5n[US[5(a,U(d%[ USUSR S35SSS2nO[ [U55nSnU(a;U(a4[XS5upxn UbURSU S [U53nXe4$U(d [U5nXe4$) ayGet the label and value list to display a condition Args: condition (Union[Clbit, ClassicalRegister], int): classical condition circuit (QuantumCircuit): the circuit that is being drawn cregbundle (bool): if set True bundle classical registers Returns: str: label to display for the condition list(str): list of 1's and 0's indicating values of condition rr*0bNr1r'r5=) boolrrintrlistrr;rrBhex) conditionrorq cond_is_bitcond_valval_bitsrrvr5rs r"get_condition_label_valr8sz)A,67K9Q< H)A, 122:8Ail&7&7%8#9:^[U5nUb+UVs/sHn[U[5(dMUPM snmOURR 5mUR R 5n/n [ UV s/sHoS4PM sn 5n U(aUb [S5eU(a!TR5 UR5 OXUbU/n /n UHGnU[T5:aU RTU5 M(U RX[T5- 5 MI U mU n[U5nUS:Xa*UR5HnU RU/5 M O[UTXX5n U(dHURSS/S9H3nUT;aTRU5 UU;dM"URU5 M5 U VVs/sH<nUVs/sH+n[!U4SjUR"55(dM)UPM- snPM> n nnTX4$s snfs sn fs snfs snnf)aZ Given a circuit, return a tuple (qubits, clbits, nodes) where qubits and clbits are the quantum and classical registers in order (based on reverse_bits or wire_order) and nodes is a list of DAGOpNodes. Args: circuit (QuantumCircuit): From where the information is extracted. reverse_bits (bool): If true the order of the bits in the registers is reversed. justify (str) : `left`, `right` or `none`. Defaults to `left`. Says how the circuit should be justified. If an invalid value is provided, default `left` will be used. idle_wires (bool): Include idle wires. Default is True. wire_order (list): A list of ints that modifies the order of the bits. Returns: Tuple(list,list,list): To be consumed by the visualizer directly. Raises: VisualizationError: if both reverse_bits and wire_order are entered. r1z@Cannot set both reverse_bits and wire_order in the same drawing.rbarrierdelay)ignorec3,># UH oT;v M g7frr)rXqqubitss r"rZ,_get_layered_instructions..s+LAKs)rrrrcopyclbitsrrreverselenr:rtopological_op_nodes _LayerSpooler idle_wiresremovereqargs)ro reverse_bitsrr wire_orderrtmeasure_arrowsrurnodesc measure_map new_qubits new_clbitsdagnodewirelayerrs @r"_get_layered_instructionsrs>%W-G!)D#ZU-C#D$$& ^^ "F E 712w78K . !cdd    CS[ !!&+.!!&s6{):";<    !C&,,.D LL$ /c66KX NN9g*>N?Dv~ d#v~ d# @ \a a[`RWu Mut+L+L(Ldu M[`E a 6  _E8HN as.H H : H H (H 6H <HHcLUSR5nURSS9 U$)zJConvert DAG layer into list of nodes sorted by node_id qiskit-terra #2802 graphcUR$r)_node_id)nds r"_sorted_nodes..sbkkr$)key)op_nodessort) dag_layerrs r" _sorted_nodesrs+ g  ' ' )E JJ)J* Lr$c[U5nSnURH$nURU5nXc:aUnXd:dM"UnM& [UR[ 5(a#[UR[ 5(dUnU$UR(aQU(a[UR[5(d[URSS5(aX[U5nU$XUS-nU$)zHGet the list of qubits drawing this gate would cover qiskit-terra #2802 rrNr*) rrr}rr!rrcargsr r?)rrr min_index max_indexqregr}spans r"_get_gate_spanrsF II  T"  I  I $''=))*TWWe2L2L K  Jtww88WTWWk[_=`=`#f+. K)a-0 Kr$c x^^[[[TUT55RUU4SjU555$)z2Return True .IFF. 'node' crosses over any 'nodes'.c3R># UHn[TUT5HnUv M M g7fr)r)rX check_noderurrs r"rZ!_any_crossover..s/G # %fj.I I #s$')rsetr intersection)rrrrs` `r"_any_crossoverrs;  N64 89FFG #G   r$cJ^\rSrSrSrU4SjrSrSrSrSr Sr S r U=r $) ri!z=Manipulate list of layer dicts for _get_layered_instructions.c>[T U]5 XlX lX0lX@lXPlX`lURRVs/sHopRRUPM snUlUR S:XaKUR5H6n[U5S- n [U5n U Hn URX5 M M8 g/n UR5HnU RU5 M U R5 U H*nSn [U5n U Hn URX5 M M, gs snf)z Create spoolrr*rN)super__init__rrr justificationrrcregslayersrraddr:r)selfrrrrrrrr current_index dag_nodesr dag_layers __class__s r"r_LayerSpooler.__init__$s    *&,59XX^^D^chhnnS)^D    ' ZZ\ #D A ))4 %DHHT1&* J ZZ\ !!),*    ' ! ))4 %DHHT1&(!Es "D<c^/nUH'nURHnURU5 M M) [U4SjU55$)z*Is any qreq in node found in any of nodes?c3@># UHoTR;v M g7fr)r)rXirs r"rZ,_LayerSpooler.is_found_in..Is6Iq ?Is)rr:re)rrr all_qargsa_nodeqargs ` r" is_found_in_LayerSpooler.is_found_inCsA F   &%6I666r$cN[URXUR5(+$)z-True .IFF. we can add 'node' to layer 'nodes')rrr)rrrs r" insertable_LayerSpooler.insertableKs!$++tD rNc3R># UHnTRSU:XdMUv M g7f)rN)r)rXrurs r"rZ0_LayerSpooler.slide_from_left..Ss%W.>s$**Q-SVBVss.>s' 'TFr1rc3B># UHnTRUv M g7fr)r)rXrurs r"rZr`s\6[sT%%c*6[s)defaultc38># UHnTU:XdM Uv M g7frr)rXrucargs r"rZrfs'W7G4SV;7Grr*r)rr!r rrr:r?maxrrrrr rr) rrr} measure_layer measure_bitinserted curr_indexlast_insertable_index index_stoprcarg_bitrs `` @r"slide_from_left_LayerSpooler.slide_from_leftOs> dggw ' 'Wd.>.>WWKH KK HJ$& !J$TWWk4@@ M \6I)6T6[6[\& zz JJD#''Wt7G7G'W#W++H5 B)-)9)9()CJC')##D$z*:;;??4j)9::,6)'!^ )%)*+2248 5  "  3t9,tT*-=>>Z(//5(2 #'!+aJ !3t9, KK  dggw ' ' #D A t// <<0=  -= (7)s AI IIcU(dURSU/5 SnOSnUnSnU[U5:aKURXU5(aO1URXU5(aUnUS-nU[U5:aMKU(aXR U5 SnODUnUS:a<URXU5(aXR U5 SnO US- nUS:aM<U(dURSU/5 gg)z>Insert node into rightmost layer as long there is no conflict.rTFNr*r1)insertrr rr:)rrr}rrrs r"slide_from_right_LayerSpooler.slide_from_rights KKD6 "HHJ$( !s4y(##Dz*:;;??4j)9::,6)'!^ s4y(%+2248"  2ot*-=>>(//5#'!+aJ !2o KKD6 "r$c[Ul[S- qURS:XaURX5 gUR X5 g)z9Add 'node' where it belongs, starting the try at 'index'.r*rN) _GLOBAL_NIDrrr!r%)rrr}s r"r_LayerSpooler.adds?$ q    '   -  ! !$ .r$)rrrrrrr) __name__ __module__ __qualname____firstlineno____doc__rr rr!r%r__static_attributes__ __classcell__)rs@r"rr!s,G2>7Q9>v#@//r$rr)r_)NT)FNTNNT);r.r collectionsrwarningsrnumpyrUqiskit.circuitrrrrr r r r r rr"qiskit.circuit.annotated_operationrrrqiskit.circuit.controlflowrqiskit.circuit.libraryrrrqiskit.circuit.toolsrqiskit.convertersr qiskit.utilsr _optionals exceptionsrr#rQrlrwrnrrrr HAS_PYLATEXrequire_in_callrrrrrrr(rrrr$r"r?s. #    ba:YY),0+ZU/p!H< B*&JZB   ''(TU)V).2  Q!h: W/DW/r$