z i7 SrSSKrSSKJr SSKJr SSKJr SSK J r SSK J r SSK Jr SS K Jr SS K Jr SS K Jr SS K Jr SS K Jr SSK Jr SSK Jr SSK Jr SSK Jr SSK Jr SSK Jr SSK Jr SSK Jr SSK Jr SSK Jr SSK Jr SSK Jr SSK J r SSK J!r! SSK J"r" SSK J#r# SSK J$r$ SSK J%r% SS K J&r& SS!K'J(r( SS"K)J*r* SS#K J+r+ SS$K,J-r- SS%K.J/r/ SS&K0J1r1 SS'K2J3r3 SS(K4J5r5 \Rl"S)S*5r7\7"1S+k\8"5S*9\7"1S,kS-S.1S*9\7"1S/k\8"5S*9\7"S01\8"5S*9\7"\8"5S1S21S*9S3.r9S4r:S5r;"S6S75r<SRS8jr=S9r>S:r?SSS0SSS;\1R4S<jrAS=rBS>rCS?rDSSS@jrE\3"SASBSCSD9STSEj5rFSUSFjrGSVSGjrH\Rl"SHSI5rISTSJ\JSK\\KSL\\/SM\LSN\I4 SOjjrM\8"\55R1SPkR\55rOSWSN\L4SQjjrPg)Xz%Common preset passmanager generators.N)Optional)SessionEquivalenceLibrary)CONTROL_FLOW_OP_NAMES)ConditionalController) PassManager)Error)BasisTranslator)Unroll3qOrMore)ConsolidateBlocks) Collect1qRuns)Collect2qBlocks)UnitarySynthesis)HighLevelSynthesis)CheckMap) GateDirection)BarrierBeforeFinalMeasurements)CheckGateDirection)TimeUnitConversion)ALAPScheduleAnalysis)ASAPScheduleAnalysis)FullAncillaAllocation)EnlargeWithAncilla) ApplyLayout)RemoveResetInZeroState) FilterOpNodes)PadDelay)InstructionDurationCheck)ConstrainedReschedule)ContainsInstruction) VF2PostLayout)VF2LayoutStopReason)VF2PostLayoutStopReason) WrapAngles)TranspilerError)Layout)OptimizationMetric)deprecate_func)_CLIFFORD_GATE_NAMES_ControlFlowState)working not_working>densesabredefaulttrivial>noner-r. stochastic lookaheadbasic>r. synthesis translatorr.alapasap) layout_methodrouting_methodtranslation_methodoptimization_methodscheduling_methodc6^[U4Sj[55$)Nc34># UH nTSU3v M g7f contains_N.0x property_sets f/home/james-whalen/.local/lib/python3.13/site-packages/qiskit/transpiler/preset_passmanagers/common.py $_has_control_flow..PsL6K|isO,6KanyrrEs`rF_has_control_flowrMOs L6KL LLc@^[U4Sj[55(+$)Nc34># UH nTSU3v M g7fr?rArBs rFrG(_without_control_flow..TsP:OQ<)A30:OrIrJrLs`rF_without_control_flowrRSsP:OPP PPrNc*\rSrSrSSjrSrSrSrg)_InvalidControlFlowForBackendWNc(Ub=[UR5S:a$[Vs/sH o3U;dM UPM snUlgUb>[U5S:a/[ U5n[Vs/sH o3U;dM UPM snUlg/Ulgs snfs snf)Nr)lenoperation_namesr unsupportedset)self basis_gatestargetops rF__init__&_InvalidControlFlowForBackend.__init__Zs  #f&<&<"="A-BW-BrPVFV-BWD   $[)9A)=k*K-B\-BrP[F[-B\D  "D  X ]s B B & B3BcURVs/sHo!SU3(dMUPM nn[U5S:Xa SUSS3$SSRSU55S 3$s snf) z3Create an error message for the given property set.r@zThe control-flow construct 'rz"' is not supported by the backend.zThe control-flow constructs [z, c38# UHn[U5v M g7fN)repr)rCr^s rFrG8_InvalidControlFlowForBackend.message..js5O2d2hhsz#] are not supported by the backend.)rYrWjoin)r[rErDfailss rFmessage%_InvalidControlFlowForBackend.messagedsu ,,N,qy_0M,N u:?1%(;]^ ^+DII5O5O,O+PQ1 1 Os AAcB^[U4SjUR55$)z/Checkable condition for the given property set.c34># UH nTSU3v M g7fr?rArBs rFrG:_InvalidControlFlowForBackend.condition..psK:JQ<)A30:JrI)rKrY)r[rEs `rF condition'_InvalidControlFlowForBackend.conditionnsK$:J:JKKKrN)rY)rAN)__name__ __module__ __qualname____firstlineno__r_rirn__static_attributes__rArNrFrTrTWs" LrNrTc \/nSnSU4SU4SU4SU4SU44H}upU S-n [U n U cMXR;dM)U R(a#USU S U S [U R5S 3- nOUSU S U S U S 3- nUR U 5 M [ 5n U R [ [SS95 U(a&U R [[U5[S95 [XV5nU R [[UR5URS95 U $)aGenerate a pass manager that, when run on a DAG that contains control flow, fails with an error message explaining the invalid options, and what could be used instead. Returns: PassManager: a pass manager that populates the ``contains_x`` properties for each of the control-flow operations, and raises an error if any of the given options do not support control flow, but a circuit with control flow is given. z.Some options cannot be used with control flow.layoutrouting translation optimization scheduling_methodz Got z='z', but valid values are .z', but the entire z stage is not supported.Frecursern)_CONTROL_FLOW_STATESr+r*listappendrrrrrrMrTrirn)r8r9r:r;r<r\r] bad_optionsristagegivenoption method_statesoutbackend_controls rF#generate_control_flow_options_checkrssO"K>G =! N# *+ ,- ()  ",V4  *C*C!C$$F82eW,DT-J_J_E`DaabcF82eW,>ugE]^   v &%& -CJJ"#8%HI (wCTUV3KHOJJeO$;$;<HaHab JrNc[5nUR[[SS95 UR[ [ U5[ S95 U$)z]Get a pass manager that always raises an error if control flow is present in a given circuit.Fr}r)rrrrrrrM)rirs rFgenerate_error_on_control_flowrs> -CJJ"#8%HIJJ$U7^?PQR JrNc\[U[5(aUR5n[U[5(aUR5n[5nUR[ [ SS95 UR[ U[S95 UR[ U[S95 U$)zGenerate a pass manager that will run the passes in ``if_present`` if the given circuit has control-flow operations in it, and those in ``if_absent`` if it doesn't.Fr}r) isinstancerto_flow_controllerrrrrrMrR) if_present if_absentrs rFif_has_control_flow_elsers*k**224 )[))002 -CJJ"#8%HIJJ$Z;LMNJJ$Y:OPQ JrNTc[5nUR[UUUSUUS95 UR[USUS[USUUS9 5 UcUcUR[ X55 U$UR[ [XSS95 U$)aGenerate an unroll >3q :class:`~qiskit.transpiler.PassManager` Args: target (Target): the :class:`~.Target` object representing the backend basis_gates (list): A list of str gate names that represent the basis gates on the backend target approximation_degree (Optional[float]): The heuristic approximation degree to use. Can be between 0 and 1. unitary_synthesis_method (str): The unitary synthesis method to use. You can see a list of installed plugins with :func:`.unitary_synthesis_plugin_names`. unitary_synthesis_plugin_config (dict): The optional dictionary plugin configuration, this is plugin specific refer to the specified plugin's documentation for how to use. hls_config (HLSConfig): An optional configuration class to use for :class:`~qiskit.transpiler.passes.HighLevelSynthesis` pass. Specifies how to synthesize various high-level objects. qubits_initially_zero (bool): Indicates whether the input circuit is zero-initialized. optimization_metric (OptimizationMetric): the :class:`~.OptimizationMetric` object that the metric used when optimizing the unrolling. Returns: PassManager: The unroll 3q or more pass manager )approximation_degreemethod min_qubits plugin_configr]NF) hls_config coupling_mapr]use_qubit_indicesequivalence_libraryr\rqubits_initially_zerooptimization_metric)r]r)rrrrselr r ) r]r\runitary_synthesis_methodunitary_synthesis_plugin_configrrr unroll_3qs rFgenerate_unroll_3qrsD I  !5+9   !# ##"7 3  v~<=  kUVWX rNcP[[U5[5[5/5$)aGenerate a layout embedding :class:`~qiskit.transpiler.PassManager` This is used to generate a :class:`~qiskit.transpiler.PassManager` object that can be used to expand and apply an initial layout to a circuit Args: coupling_map (Union[CouplingMap, Target): The coupling map for the backend to embed the circuit to. Returns: PassManager: The embedding passmanager that assumes the layout property set has been set in earlier stages )rrrr)rs rFgenerate_embed_passmanagerrs$ -l;=O=QS^S`a bbrNc2USSL=(a US(+$)zReturn ``True`` if the first attempt at layout has been checked and found to be imperfect. In this case, perfection means "does not require any swap routing".is_swap_mappedNrArLs rF_layout_not_perfectrs# ( ) 5 \lK[>\:\\rNcHUSSL=(a US[RL$)NVF2PostLayout_stop_reason)r"SOLUTION_FOUNDrLs rF_apply_post_layout_conditionrs2 01= ` 4 59P9_9_ _rNc ^U4Sjn[5n UbU R[USS95 OU R[USS95 Sn U(a#U R[[ SS9U/U S95 OU R[X S95 U=(a Un UbPU (aIU R[[ UUUUSS 9US95 U R[[ 5[S95 S n U R[U 5/5 U $) aGenerate a routing :class:`~qiskit.transpiler.PassManager` Args: routing_pass (TransformationPass): The pass which will perform the routing target (Target): the :class:`~.Target` object representing the backend coupling_map (CouplingMap): The coupling map of the backend to route for vf2_call_limit (int): The internal call limit for the vf2 post layout pass. If this is ``None`` or ``0`` the vf2 post layout will not be run. seed_transpiler (int): Sets random seed for the stochastic parts of the transpiler. This is currently only used for :class:`.VF2PostLayout` and the default value of ``-1`` is strongly recommended (which is no randomization). If a value of ``None`` is provided this will seed from system entropy. check_trivial (bool): If set to true this will condition running the :class:`~.VF2PostLayout` pass after routing on whether a trivial layout was tried and was found to not be perfect. This is only needed if the constructed pass manager runs :class:`~.TrivialLayout` as a first layout attempt and uses it if it's a perfect layout (as is the case with preset pass manager level 1). use_barrier_before_measurement (bool): If true (the default) the :class:`~.BarrierBeforeFinalMeasurements` transpiler pass will be run prior to the specified pass in the ``routing_pass`` argument. vf2_max_trials (int): The maximum number of trials to run VF2 when evaluating the vf2 post layout pass. If this is ``None`` or ``0`` the vf2 post layout will not be run. Returns: PassManager: The routing pass manager cn>T(a[U5(aUSnUbU[R:wagg)NVF2Layout_stop_reasonTF)rr!r)rEvf2_stop_reason check_trivials rF_run_post_layout_condition@generate_routing_passmanager.._run_post_layout_conditionGs8 3L A A*+BCO&/=P=_=_*_rNrouting_not_needed)property_set_fieldcUS(+$)NrrArLs rF_swap_condition5generate_routing_passmanager.._swap_conditionVs 4555rN5qiskit.transpiler.internal.routing.protection.barrierlabelrF)seed call_limit max_trialsstrict_directionc URS:g$)Nrr)nodes rF filter_fn/generate_routing_passmanager..filter_fnxszzTTTrN) rrrrrr rrr) routing_passr]rvf2_call_limitseed_transpilerruse_barrier_before_measurementvf2_max_trialsrrwris_vf2_fully_boundedrs ` rFgenerate_routing_passmanagerrs TmG x;OPQx AUVW6& !2U!  *   ,\UV)._direction_condition#$9:: :rNr)rrrrrr)r]rremove_reset_in_zeropre_optrs rFgenerate_pre_op_passmanagerrsc.mG),FG ;  !|;<.  -/0 NrNc fUcUc [/5$US:Xa7[[X5n [UUUUUUS9[ UUUS[UUS9U /n U /n GO9US:Xa[ U5S/-n [U UUUUSS9[ UUSS[U U[ RS 9[[U S5[5[SSUSS 9[S S S 0S9[/SQUUUSS SS9[[X5/n [[X5n U /n OUS:Xa}[UUUUUSUS9[ UUUSUSUS9[XS9[5[5[XUS9[UUUUUUS9[ UUUSUUS9/n [5[XUS9[UUUUUUS9/n O[SUS35eU(aUR(aUbSURSS9(a?U R[!X@S95 Sn U R[#[%X@S9/U -U S95 Ub/UR'5(aU R[)U55 [U 5$)aGenerate a basis translation :class:`~qiskit.transpiler.PassManager` Args: target (Target): the :class:`~.Target` object representing the backend basis_gates (list): A list of str gate names that represent the basis gates on the backend target method (str): The basis translation method to use approximation_degree (Optional[float]): The heuristic approximation degree to use. Can be between 0 and 1. coupling_map (CouplingMap): the coupling map of the backend in case synthesis is done on a physical circuit. The directionality of the coupling_map will be taken into account if pulse_optimize is True/None and natural_direction is True/None. unitary_synthesis_plugin_config (dict): The optional dictionary plugin configuration, this is plugin specific refer to the specified plugin's documentation for how to use. unitary_synthesis_method (str): The unitary synthesis method to use. You can see a list of installed plugins with :func:`.unitary_synthesis_plugin_names`. hls_config (HLSConfig): An optional configuration class to use for :class:`~qiskit.transpiler.passes.HighLevelSynthesis` pass. Specifies how to synthesize various high-level objects. qubits_initially_zero (bool): Indicates whether the input circuit is zero-initialized. Returns: PassManager: The basis translation pass manager Raises: TranspilerError: If the ``method`` kwarg is not a valid value Nr5)rrrrr]T)rrr]rrr\r clifford_tu)r\rrrrr])rrr]rrr\rr)r\r]rforce_consolidateclifford max_qubitsrb)rr)httdgsk)r\rrrrrr]r4r)rrrrrr])rrr]rr\rr)r]r\)r\r]r)rrr]rr\rzInvalid translation method r|)rrcUS(+$rrArLs rFr>generate_translation_passmanager.._direction_conditionyrrNr)rr rrrrr&COUNT_Tr r r r r$ is_symmetricget_non_global_operation_namesrrrrhas_angle_boundsr#)r]r\rrrrrrrr5unrollfix_1qextended_basis_gatesrs rF generate_translation_passmanagerrsTv~2 $S+>  %9)=/   %)"&$''&;  ) , <  $K0C58 0%9)=/   %)"&$'0&;$6$>$>  C!5t < O  %9"&   J|Q>O P -%9)=  C 5s: z%S+>  ;  %9)=/  %)"&'&;  & B   O 'Ma  '%9)=/   %)"&'&;  G+ Z O 'Ma  '%9)=/     ;F81EFF \66vDDVZD[ (EF ;  !|;._contains_delays 01 1rNdelayrrbc US$)Nreschedule_requiredrArLs rF_require_alignment/generate_scheduling.._require_alignments 56 6rN)acquire_alignmentpulse_alignmentr])r] durations)rrrrrKeyErrorr$rr granularity min_lengthrrrrr) instruction_durationsr<timing_constraintsr]rz schedulerexrrs rFgenerate_schedulingrs"J)#7(#7  ,-BRS ]   i:;P` a  2 -g67 !"#8HTc  &&!+  ( (A -  / /1 4  - - 2 7  $"4"F"F 2 B B    !%&8&J&J$6$F$F! -   (&RS [ ]!$>?P>QQR"STZ\ \ ]sE&& F0FF VF2Limits)rroptimization_levelr8initial_layout exact_matchreturnc.[SS5nUcUcUS;a [SS5nOUS:Xa [SS5nU(aV[URbURS-=(d S OSURbURS-=(d S OS5nU$) zGet the VF2 limits for VF2-based layout passes. Returns: VF2Limits: An namedtuple with optional elements ``call_limit`` and ``max_trials``. N>rbiPi riidrb)rrr)rr8rrlimitss rFget_vf2_limitsr stT "F!7  'F 1 $F 5;5F5F5R&##s*0qX\5;5F5F5R&##s*0qX\F MrN>rrrresetbarriermeasurecUb[UR5nOUb [U5nO [5nUb SU;aSU;agUR[5$)a" Checks whether the given basis set can be considered as Clifford+T. For this we require that: 1. The set only contains Clifford+T gates, 2. The set contains either T or Tdg gate or both. In particular, these conditions guarantee that the empty basis set is not considered as Clifford+T. rrF)rZrXissubset_CLIFFORD_T_BASIS)r\r]basiss rFis_clifford_t_basisrsXF**+  K #["8uK?W >>+ ,,rN)NNNNNrAN)NNFTN)NNF)Nr5NNr.NNTrd)NN)Q__doc__ collectionstypingr"qiskit.circuit.equivalence_libraryrrqiskit.circuit.controlflowr#qiskit.passmanager.flow_controllersrqiskit.transpiler.passmanagerrqiskit.transpiler.passesrr r r r r rrrrrrrrrrrrrrrrrrr *qiskit.transpiler.passes.layout.vf2_layoutr!/qiskit.transpiler.passes.layout.vf2_post_layoutr"r#qiskit.transpiler.exceptionsr$qiskit.transpiler.layoutr%%qiskit.transpiler.optimization_metricr& qiskit.utilsr':qiskit.quantum_info.operators.symplectic.clifford_circuitsr( namedtupler)rZrrMrRrTrrrCOUNT_2Qrrrrrrrrrintstrboolr unionrrrArNrFr,sf,O<E5*4362457-2C7799:70;2-=:82JS/8+D'[ **+>@Z[ '8ce(:V]H^,6E-i[ceT*35vvFVW  MQLL: .b  &$(*33@F c ] #'`F  5% F &$([|JZ  " ";0L M $('+ C=V$   H,-338>>?TU -$-rN