z i nSrSSKJr SSKJr SSKJrJrJr SSK J r SSK J r SSK Jr "S S \5rg ) z0Padding pass to insert Delay to the empty slots.)Qubit)Delay) DAGCircuitDAGNode DAGOutNode)Target)InstructionDurations) BasePaddingc h^\rSrSrSrSS\S\S\4U4SjjjrS\ S\ S \ S \ S \ S \ 4 S jr SrU=r$)PadDelayu/Padding idle time with Delay instructions. Consecutive delays will be merged in the output of this pass. .. plot:: :include-source: :nofigs: from qiskit import QuantumCircuit from qiskit.transpiler import InstructionDurations durations = InstructionDurations([("x", None, 160), ("cx", None, 800)]) qc = QuantumCircuit(2) qc.delay(100, 0) qc.x(1) qc.cx(0, 1) The ASAP-scheduled circuit output may become .. code-block:: text ┌────────────────┐ q_0: ┤ Delay(160[dt]) ├──■── └─────┬───┬──────┘┌─┴─┐ q_1: ──────┤ X ├───────┤ X ├ └───┘ └───┘ Note that the additional idle time of 60dt on the ``q_0`` wire coming from the duration difference between ``Delay`` of 100dt (``q_0``) and ``XGate`` of 160 dt (``q_1``) is absorbed in the delay instruction on the ``q_0`` wire, i.e. in total 160 dt. See :class:`BasePadding` pass for details. fill_very_endtarget durationsc,>[TU]X#S9 Xlg)a;Create new padding delay pass. Args: fill_very_end: Set ``True`` to fill the end of circuit with delay. target: The :class:`~.Target` representing the target backend. If it is supplied and does not support delay instruction on a qubit, padding passes do not pad any idle time of the qubit. )rrN)super__init__r)selfrrr __class__s o/home/james-whalen/.local/lib/python3.13/site-packages/qiskit/transpiler/passes/scheduling/padding/pad_delay.pyrPadDelay.__init__<s <*dagqubitt_startt_end next_node prev_nodecUR(d[U[5(agXC- nURX[ XqR 5U5 g)N)r isinstancer_apply_scheduled_opr_unit)rrrrrrr time_intervals r_pad PadDelay._padMs?!!jJ&G&G     u]II/NPUVr)r)TNN)__name__ __module__ __qualname____firstlineno____doc__boolrr rrrintrr%__static_attributes__ __classcell__)rs@rr r s!J#*. +++( ++" W  W W W  W  W W Wrr N)r+qiskit.circuitrqiskit.circuit.delayrqiskit.dagcircuitrrrqiskit.transpiler.targetr'qiskit.transpiler.instruction_durationsr base_paddingr r rrr7s/7 &==+H%BW{BWr