z i2)SrSSKJr SSKJr SSKJr SSKJr SSK J r SSK J r SSK JrJrJr SS KJr SS KJr SS KJr "S S \5rg)z,Rescheduler pass to adjust node start times.) annotations) Generator)Gate)Delay)Measure)Reset) DAGCircuit DAGOpNode DAGOutNode) AnalysisPass)TranspilerError)Targetcl^\rSrSrSrSS U4Sjjjr\S Sj5rS SjrS Sjr Sr U=r $) ConstrainedRescheduleu3Rescheduler pass that updates node start times to conform to the hardware alignments. This pass shifts DAG node start times previously scheduled with one of the scheduling passes, e.g. :class:`ASAPScheduleAnalysis` or :class:`ALAPScheduleAnalysis`, so that every instruction start time satisfies alignment constraints. Examples: We assume executing the following circuit on a backend with 16 dt of acquire alignment. .. code-block:: text ┌───┐┌────────────────┐┌─┐ q_0: ┤ X ├┤ Delay(100[dt]) ├┤M├ └───┘└────────────────┘└╥┘ c: 1/════════════════════════╩═ 0 Note that delay of 100 dt induces a misalignment of 4 dt at the measurement. This pass appends an extra 12 dt time shift to the input circuit. .. code-block:: text ┌───┐┌────────────────┐┌─┐ q_0: ┤ X ├┤ Delay(112[dt]) ├┤M├ └───┘└────────────────┘└╥┘ c: 1/════════════════════════╩═ 0 Notes: Your backend may execute circuits violating these alignment constraints. However, you may obtain erroneous measurement result because of the untracked phase originating in the instruction misalignment. c>[TU]5 XlX lUb>UR 5UlX0lUR UlURUlgg)acCreate new rescheduler pass. The alignment values depend on the control electronics of your quantum processor. Args: acquire_alignment: Integer number representing the minimum time resolution to trigger acquisition instruction in units of ``dt``. pulse_alignment: Integer number representing the minimum time resolution to trigger gate instruction in units of ``dt``. target: The :class:`~.Target` representing the target backend, if ``target`` is specified then this argument will take precedence and ``acquire_alignment`` and ``pulse_alignment`` will be ignored. N)super__init__ acquire_align pulse_align durationstargetacquire_alignmentpulse_alignment)selfrrr __class__s s/home/james-whalen/.local/lib/python3.13/site-packages/qiskit/transpiler/passes/scheduling/alignments/reschedule.pyrConstrainedReschedule.__init__@sX& .*  #--/DN K!'!9!9D %55D  c#r# URU5Hn[U[5(aMUv M g7f)zGet next non-delay nodes. Args: dag: DAG circuit to be rescheduled with constraints. node: Current node. Returns: A list of non-delay successors. N) successors isinstancer )clsdagnode next_nodes r_get_next_gate$ConstrainedReschedule._get_next_gate\s,-Ii44.s(7 7c URSnURRSS5n[UR[5(a UR nO[UR[ [45(a URnOV[UR[5(d[URSS5(aSnO[S[U5S35eX2nUb&X2U-nUS:wa[SXW- 5nOSnXh- nXcU'URb_URRURUR V s/sHoR#U 5R$PM sn 5n Xj-n O+UR&S :XaXbRR(-n OUn [+UR 5n [UR[ [45(aU n [+UR,5nO Sn [+5nUR/X5HnX?n[+UR 5n[UR[ [45(aUU-n[+UR,5nO Sn[+5n[1U U-5(aU U- nOSn[1UU-5(aU U- nOSn[UU5nX?U-X?'M gs sn f![a Sn GNkf=f) aUpdate the start time of the current node to satisfy alignment constraints. Immediate successors are pushed back to avoid overlap and will be processed later. .. note:: This logic assumes the all bits in the qregs and cregs synchronously start and end, i.e. occupy the same time slot, but qregs and cregs can take different time slot due to classical I/O latencies. Args: dag: DAG circuit to be rescheduled with constraints. node: Current node. node_start_timeclbit_write_latencyr _directiveFNzUnknown operation type for .delay) property_setgetr"oprrrrrrgetattrr reprmaxrrqargsfind_bitindexnamedurationsetcargsr'any)rr$r%r*r+ alignmentthis_t0 misalignmentshiftxr9new_t1q this_qubitsnew_t1c this_clbitsr&next_t0q next_qubitsnext_t0c next_clbits qreg_overlap creg_overlapoverlaps r_push_node_back%ConstrainedReschedule._push_node_backks++,=>"//334I1M dggt $ $((I '5!1 2 2**I  ' '7477L%+P+PI!$?T |1"MN N!'  *09>--dggW[WaWa7bWaRS Q8M8MWa7bc(G YY' ! 0 00GG$**o dgg/ 0 0Gdjj/KG%K,,S7I&1Hioo.K),,%(899#&99!)//2 !e ;,--&1  ;,--&1  , 5G)8)Cg)MO &18'8c"  s$.K $K -K K K K cZSUR;a0[SURSURRS35eURSnUR 5HHnUR U5nUc[S[U5S35eUS:XaM7URX5 MJ g) aRun rescheduler. This pass should perform rescheduling to satisfy: - All DAGOpNode nodes (except for compiler directives) are placed at start time satisfying hardware alignment constraints. - The end time of a node does not overlap with the start time of successor nodes. Assumptions: - Topological order and absolute time order of DAGOpNode are consistent. - All bits in either qargs or cargs associated with node synchronously start. - Start time of qargs and cargs may different due to I/O latency. Based on the configurations above, the rescheduler pass takes the following strategy: 1. The nodes are processed in the topological order, from the beginning of the circuit (i.e. from left to right). For every node (including compiler directives), the function ``_push_node_back`` performs steps 2 and 3. 2. If the start time of the node violates the alignment constraint, the start time is increased to satisfy the constraint. 3. Each immediate successor whose start_time overlaps the node's end_time is pushed backwards (towards the end of the wire). Note that at this point the shifted successor does not need to satisfy the constraints, but this will be taken care of when that successor node itself is processed. 4. After every node is processed, all misalignment constraints will be resolved, and there will be no overlap between the nodes. Args: dag: DAG circuit to be rescheduled with constraints. Raises: TranspilerError: If circuit is not scheduled. r*zThe input circuit zD is not scheduled. Call one of scheduling passes before running the z pass.NzStart time of z^ is not found. This node is likely added after this circuit is scheduled. Run scheduler again.r) r/r r8r__name__topological_op_nodesr0r3rM)rr$r*r% start_times rrunConstrainedReschedule.runsH D$5$5 5!$SXXJ/&&*nn&=&=%>fF  ++,=>,,.D(,,T2J!%$T$ZL1FF Q   +/r)rrrr)rUN)rintrrVrr)r$r r%r returnz Generator[DAGOpNode, None, None])r$r r%r )r$r ) rP __module__ __qualname____firstlineno____doc__r classmethodr'rMrS__static_attributes__ __classcell__)rs@rrrs`"L"#  666 668    TNl:,:,rrN)r[ __future__rcollections.abcrqiskit.circuit.gaterqiskit.circuit.delayrqiskit.circuit.measurerqiskit.circuit.resetrqiskit.dagcircuitr r r qiskit.transpiler.basepassesr qiskit.transpiler.exceptionsr qiskit.transpiler.targetrrrrrjs93"%$&*&??58+`,L`,r