z i.GSrSSKJr SSKrSSKrSSKrSSKrSSKJrJ r J r SSK J r SSK Jr SSKJr SSKJr \R&"\5r"S S \5rS r"S S \5rg)zNVF2PostLayout pass to find a layout after transpile using subgraph isomorphism)EnumN) PyDiGraph vf2_mappingPyGraph)Layout) AnalysisPass)TranspilerError) vf2_utilsc(\rSrSrSrSrSrSrSrSr g) VF2PostLayoutStopReason z$Stop reasons for VF2PostLayout pass.zsolution foundzno better solution foundznonexistent solutionz>2q gates in basisN) __name__ __module__ __qualname____firstlineno____doc__SOLUTION_FOUNDNO_BETTER_SOLUTION_FOUNDNO_SOLUTION_FOUND MORE_THAN_2Q__static_attributes__ri/home/james-whalen/.local/lib/python3.13/site-packages/qiskit/transpiler/passes/layout/vf2_post_layout.pyr r s.%N9.'Lrr c[U[5(aURUR55$[U5R U5$)N) isinstanceset issupersetkeysissubset)node_anode_bs r _target_matchr#)s?&#  //6{##F++rcH^\rSrSrSrSU4SjjrSrSrSrU=r $) VF2PostLayout4aM A pass for improving an existing Layout after transpilation of a circuit onto a Coupling graph, as a subgraph isomorphism problem, solved by VF2++. Unlike the :class:`~.VF2Layout` transpiler pass which is designed to find an initial layout for a circuit early in the transpilation pipeline this transpiler pass is designed to try and find a better layout after transpilation is complete. The initial layout phase of the transpiler doesn't have as much information available as we do after transpilation. This pass is designed to be paired in a similar pipeline as the layout passes. This pass will strip any idle wires from the circuit, use VF2 to find a subgraph in the coupling graph for the circuit to run on with better fidelity and then update the circuit layout to use the new qubits. The algorithm used in this pass is described in `arXiv:2209.15512 `__. If a solution is found that means there is a lower error layout available for the circuit. If a solution is found the layout will be set in the property set as ``property_set['post_layout']``. However, if no solution or no better solution is found, no ``property_set['post_layout']`` is set. The stopping reason is set in ``property_set['VF2PostLayout_stop_reason']`` in all the cases and will be one of the values enumerated in ``VF2PostLayoutStopReason`` which has the following values: * ``"solution found"``: If a solution was found. * ``"no better solution found"``: If the initial layout of the circuit is the best solution. * ``"nonexistent solution"``: If no solution was found. * ``">2q gates in basis"``: If VF2PostLayout can't work with the basis of the circuit. By default, this pass will construct a heuristic scoring map based on the error rates in the provided ``target``. However, analysis passes can be run prior to this pass and set ``vf2_avg_error_map`` in the property set with a :class:`~.ErrorMap` instance. If a value is ``NaN`` that is treated as an ideal edge For example if an error map is created as:: from qiskit.transpiler.passes.layout.vf2_utils import ErrorMap error_map = ErrorMap(3) error_map.add_error((0, 0), 0.0024) error_map.add_error((0, 1), 0.01) error_map.add_error((1, 1), 0.0032) that represents the error map for a 2 qubit target, where the avg 1q error rate is ``0.0024`` on qubit 0 and ``0.0032`` on qubit 1. Then the avg 2q error rate for gates that operate on (0, 1) is 0.01 and (1, 0) is not supported by the target. This will be used for scoring if it's set as the ``vf2_avg_error_map`` key in the property set when :class:`~.VF2PostLayout` is run. cx>[TU]5 XlX0lX@lX`lX lXPlSUlg)aInitialize a ``VF2PostLayout`` pass instance Args: target (Target): A target representing the backend device to run ``VF2PostLayout`` on. seed (int): Sets the seed of the PRNG. -1 Means no node shuffling. call_limit (int): The number of state visits to attempt in each execution of VF2. time_limit (float): The total time limit in seconds to run ``VF2PostLayout`` strict_direction (bool): Whether the pass is configured to follow the strict direction in the coupling graph. If this is set to false, the pass will treat any edge in the coupling graph as a weak edge and the interaction graph will be undirected. For the purposes of evaluating layouts the avg error rate for each qubit and 2q link will be used. This enables the pass to be run prior to basis translation and work with any 1q and 2q operations. However, if ``strict_direction=True`` the pass expects the input :class:`~.DAGCircuit` object to :meth:`~.VF2PostLayout.run` to be in the target set of instructions. max_trials (int): The maximum number of trials to run VF2 to find a layout. A value of ``0`` (the default) means 'unlimited'. Raises: TypeError: At runtime, if ``target`` isn't provided. N) super__init__target call_limit time_limit max_trialsseedstrict_direction avg_error_map)selfr*r.r+r,r/r- __class__s rr)VF2PostLayout.__init__ds8B  $$$ 0!rc ZURc [S5eUR(dGURSUlURc&[ R "URS5Ul[ R"XR5nUc[RURS'gUup4pVUR(aDU(a=[U5S:a[RURS'gUR5 [ R"X45n[ R"U5nURRcgUR(a [!SS9n O [#SS9n Sn SURR;a//S.n URR%S5Hn URR'U 5n [(R*"U 5(a*U SR-U 5 U S R-U 5 McU R.n X;dMvXR-U 5 M /n[1URR.5HQn[3URR%U455nU bUR7U S5 UR-U5 MS U R9U5 URRHjn[U5nUS :XdM[3URR%U55nU bUR7U S 5 U R;US USU5 Ml [=U R?55nUR(d[3[@RBREURR55n[3U RG55RIU5nU(aU RK[=U55 [LROS 5 UR(a4UR(a#[QU U[R[RS SSURTS 9nO[QU US SSURTS9nSnUR(aJ[W[YURZ5VVs0sH unnUU_M snn5nUR]UUUU5nOe[YURZ5VVs0sHunnUU;dMUUU_M nnn[ R^"URUUUUURUUS9nUn[Rn[LROSU5 [bRb"5nS nUGHn US- n[LROSU5 U Re5V!V"s0sH un!n"U"UU!_M n#n!n"UR(aG[WU#Re5V$V%s0sH un$n%UU$U%_M sn%n$5n&UR]U&XEU5n'O/[ R^"URU#UUUURUUS9n'[LROSUU'5 U'U:a`[WU#Re5V$V%s0sH un$n%UU$U%_M sn%n$5n&[LROSU&U'UU5 U&nU'n[RfnURh(a3UURh:a#[LROSUURh5 O`[bRb"5U- n(URjcGMU(URj:dGM[LROSU(URj5 O U[Rf:XGa2[ Rl"UUU Ro5UUR5nURSn)U)b[U)5[U5:aURq5n*[3U*Rs55n+[U 5n URZHcn[U5[U)5:Xa OJUU*;dM%[1U 5H/nUU+;dM U+RuU5 URuUU5 Ma Me [ Rv"XRU5URS'OUc[R`nUURS'g![4a [35nGNWf=fs snnfs snnf![4a [R`URS'gf=fs sn"n!fs sn%n$fs sn%n$f)zrun the layout methodNz=A target must be specified or a coupling map must be providedvf2_avg_error_mapVF2PostLayout_stop_reasonF) multigraph)r7r9rz+Running VF2 to find post transpile mappingsT) node_matcher edge_matchersubgraphid_orderinducedr+)r<r=r>r+) edge_listbit_listzInitial layout has score %szRunning trial: %szTrial %s has score %szAFound layout %s has a lower score (%s) than previous best %s (%s)z'Trial %s is >= configured max trials %sz?VFPostLayout has taken %s which exceeds configured max time: %slayout post_layout)=T=a=aD  9 : MSJ%>  Z:"+DD!!"=>    $33HP%55h? ;;   $    E2H%0H  4;;$$ $BJkk;;DA KK::2> ??9--qM((,qM((,!*!5!5J!/".55b9Bt{{--.A DKKAA1$GH% Z]+ OOE "/ )[[&&E5zH1}$++??FG)JJz!}-!!%(E!Hc:'--/0 $$ !>!>t{{?P?P!QRNH1134??OI**4 ?; BC ;;400"**?? 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