z iNSrSSKJr SSKJr SSKJr SSKJr "SS\5r g) zGAllocate all idle nodes from the coupling map as ancilla on the layout.)QuantumRegister) AnalysisPassTranspilerError)TargetcB^\rSrSrSrU4SjrSr\S5rSr U=r $)FullAncillaAllocationaAllocate all idle nodes from the coupling map or target as ancilla on the layout. A pass for allocating all idle physical qubits (those that exist in coupling map or target but not the dag circuit) as ancilla. It will also choose new virtual qubits to correspond to those physical ancilla. Note: This is an analysis pass, and only responsible for choosing physical ancilla locations and their corresponding virtual qubits. A separate transformation pass must add those virtual qubits to the circuit. c>[TU]5 [U[5(a&XlURR 5UlO SUlXlSUlg)zFullAncillaAllocation initializer. Args: coupling_map (Union[CouplingMap, Target]): directed graph representing a coupling map. Nancilla)super__init__ isinstancertargetbuild_coupling_map coupling_map ancilla_name)selfr __class__s q/home/james-whalen/.local/lib/python3.13/site-packages/qiskit/transpiler/passes/layout/full_ancilla_allocation.pyrFullAncillaAllocation.__init__#sL  lF + +&K $ > > @D DK , %cURRS5nUc [S5eUR5nUR 5nU(aJ[ R U[UR55 [[[U5S-55nO/nUVs/sH ofU;dM UPM nnURbNURRb7[URR5Vs/sH ofU;dM UPM nnO>UR(a-URRVs/sH ofU;dM UPM nnU(aUR UR";a+[$R&"[)U5UR 5nO[%[)U5UR S9n[+U5HupXURSU 'M URSR-U5 U$s snfs snfs snf)aFRun the FullAncillaAllocation pass on `dag`. Extend the layout with new (physical qubit, virtual qubit) pairs. The dag signals which virtual qubits are already in the circuit. This pass will allocate new virtual qubits such that no collision occurs (i.e. Layout bijectivity is preserved) The coupling_map and layout together determine which physical qubits are free. Args: dag (DAGCircuit): circuit to analyze Returns: DAGCircuit: returns the same dag circuit, unmodified Raises: TranspilerError: If there is not layout in the property set or not set at init time. layoutz;FullAncillaAllocation pass requires property_set["layout"].)name) property_setgetrget_virtual_bitsget_physical_bitsr validate_layoutsetqubitslistrangemaxr num_qubitsrphysical_qubitsrqregsr_new_with_prefixlen enumerate add_register) rdagr virtual_bits physical_bitslayout_physical_qubitsqidle_physical_qubitsqregidxidle_qs rrunFullAncillaAllocation.run2s&""&&x0 >!"_` `..0 002  ! 1 1,CJJ P%)%M0BQ0F*G%H "%' "+A\+AamE[+A\ ;; "t{{'='='I !7!78$8a] 6:i!!(+F3 ?   h ' 4 4T : - ]$$s$! H.H; HH: H H c6UHnX!;dM [S5e g)z_ Checks if all the qregs in ``layout_qregs`` already exist in ``dag_qregs``. Otherwise, raise. zSFullAncillaAllocation: The layout refers to a qubit that does not exist in circuit.Nr) layout_qubits dag_qubitsr4s rr!%FullAncillaAllocation.validate_layoutjs& "D%%6"r)rrr) __name__ __module__ __qualname____firstlineno____doc__rr7 staticmethodr!__static_attributes__ __classcell__)rs@rr r s'  &6p  rr N) rAqiskit.circuitrqiskit.transpiler.basepassesrqiskit.transpiler.exceptionsrqiskit.transpiler.targetrr rrrJs%N*58+_L_r