z i3BSrSSKJr SSKJr SSKJr "SS\5rg)zBit-flip Oracle object.) annotations)Gate)BooleanExpressionc`^\rSrSrSrSSU4SjjjrSr\S Sj5rSr U=r $) BitFlipOracleGatea4Implements a bit-flip oracle The Bit-flip Oracle Gate object constructs circuits for any arbitrary input logical expressions. A logical expression is composed of logical operators `&` (logical `AND`), `|` (logical `OR`), `~` (logical `NOT`), and `^` (logical `XOR`). as well as symbols for literals (variables). For example, `'a & b'`, and `(v0 | ~v1) & (~v2 & v3)` are both valid string representation of boolean logical expressions. A bit-flip oracle for a boolean function `f(x)` performs the following quantum operation: .. math:: |x\rangle|y\rangle \mapsto |x\rangle|f(x)\oplus y\rangle For convenience, this oracle, in addition to parsing arbitrary logical expressions, also supports input strings in the `DIMACS CNF format `__, which is the standard format for specifying SATisfiability (SAT) problem instances in `Conjunctive Normal Form (CNF) `__, which is a conjunction of one or more clauses, where a clause is a disjunction of one or more literals. See :meth:`qiskit.circuit.library.bit_flip_oracle.BitFlipOracleGate.from_dimacs_file`. From 16 variables on, possible performance issues should be expected when using the default synthesizer. c>Uc1[U[5(a[U5S:aUSSS-OUnOSn[U[5(a [XS9nXl[ TU]SURRS-/US9 g) a Args: expression: A Python-like boolean expression string or a `BooleanExpression` object. var_order: A list with the order in which variables will be created. (default: by appearance) label: A label for the gate to display in visualizations. Per default, the label is set to display the textual represntation of the boolean expression (truncated if needed) Nz...zBoolean Expression) var_orderzBit-flip Oracle)name num_qubitsparamslabel) isinstancestrlenrboolean_expressionsuper__init__num_bits)self expressionr r __class__s `/home/james-whalen/.local/lib/python3.13/site-packages/qiskit/circuit/library/bit_flip_oracle.pyrBitFlipOracleGate.__init__5s =*c**58_r5ICR50z, j# & &*:KJ", "..77!;  c@URRSS9Ulg)z*Defined by the synthesized bit-flip oraclebit) circuit_typeN)rsynth definition)rs r_defineBitFlipOracleGate._defineTs1177U7Krc>[R"U5nU"U5$)aCreate a BitFlipOracleGate from the string in the DIMACS format. It is possible to build a BitFlipOracleGate from a file in `DIMACS CNF format `__, which is the standard format for specifying SATisfiability (SAT) problem instances in `Conjunctive Normal Form (CNF) `__, which is a conjunction of one or more clauses, where a clause is a disjunction of one or more literals. The following is an example of a CNF expressed in the DIMACS format: .. code:: text c DIMACS CNF file with 3 satisfying assignments: 1 -2 3, -1 -2 -3, 1 2 -3. p cnf 3 5 -1 -2 -3 0 1 -2 3 0 1 2 -3 0 1 -2 -3 0 -1 2 3 0 The first line, following the `c` character, is a comment. The second line specifies that the CNF is over three boolean variables --- let us call them :math:`x_1, x_2, x_3`, and contains five clauses. The five clauses, listed afterwards, are implicitly joined by the logical `AND` operator, :math:`\land`, while the variables in each clause, represented by their indices, are implicitly disjoined by the logical `OR` operator, :math:`\lor`. The :math:`-` symbol preceding a boolean variable index corresponds to the logical `NOT` operator, :math:`\lnot`. Character `0` (zero) marks the end of each clause. Essentially, the code above corresponds to the following CNF: :math:`(\lnot x_1 \lor \lnot x_2 \lor \lnot x_3) \land (x_1 \lor \lnot x_2 \lor x_3) \land (x_1 \lor x_2 \lor \lnot x_3) \land (x_1 \lor \lnot x_2 \lor \lnot x_3) \land (\lnot x_1 \lor x_2 \lor x_3)`. Args: filename: A file in DIMACS format. Returns: BitFlipOracleGate: A quantum gate with a bit-flip oracle. )rfrom_dimacs_file)clsfilenameexprs rr&"BitFlipOracleGate.from_dimacs_fileXsZ!11(;4yr)rr")NN)rzstr | BooleanExpressionr zlist[str] | Nonerz str | NonereturnNone)r(rr+r) __name__ __module__ __qualname____firstlineno____doc__rr# classmethodr&__static_attributes__ __classcell__)rs@rrrs[B'+  + $      >L--rrN)r1 __future__rqiskit.circuitr+qiskit.synthesis.boolean.boolean_expressionrrrrr9s!"Ippr